The present invention relates in general to data processing systems, and in particular, to Array Built-In Self Test of integrated circuits implemented in a processor incorporated in the data processing system.
In general, integrated circuit arrays (e.g. memory arrays) are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well know and widely used system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself This Array Built-In Self Test (ABIST) technology allows high speed testing of the array without having to force correspondence between the array and the input/output connections to the chip itself. In order to provide high speed testing and to confine the test system to a minimum area of the chip, early ABIST systems had hardwired circuits for generation of test data, generation of control sequences, and test data gathering. However changes in the structure and types of arrays in integrated circuit chips required special hardware for each type of array tested and for the varied expected failure conditions. Improvements in ABIST followed when the control sequences and test patterns were generated by built-in programmable ABIST (PABIST) systems. PABIST systems allowed a programmable controller with an instruction storage space to be loaded with instructions. Instructions were scanned in via a level sensitive scan device (LSSD).
A PABIST system tests an array by executing a sequence of instructions to generate test patterns for an array, testing results and scanning out the test results also using a LSSD. With a suitable instruction set, control of how the sequence was executed and incorporating methods for changing instruction sequence, a sophisticated and powerful PABIST was possible. Programmability enabled a standard test system to be integrated onto integrated circuits for testing a variety of array types and variety of failure modes. PABIST also allowed new tests to be developed and used without modifying the hardwired circuits of the integrated circuit chip.
Early programmable PABIST systems allowed a wider variety of tests to be run than was previously possible with hardwired test logic. An array test designer did not have to anticipate all types of failures and all desired test sequences. To test a specific array, PABIST controllers could be loaded with instruction sequences that when executed would write data to and read data from the array. The simplest test in this type of system would be to compare what is written to a specific address of the array with what was read from the same address of the array. In this case what was written to an address was what was xe2x80x9cexpectedxe2x80x9d when a read was executed at the corresponding same address. The input/output data was compared in a data comparator that compared all the bits. Different patterns were written to and read from the array and a pass/fail result was possible after a particular test pattern was executed.
This type of pass/fail indicator is highly desirable for diagnostics, and is essential if capturing the failed addresses is needed for repairable arrays. The failure modes for present arrays require test data patterns with more complexity both in the static bit patterns (what was written in adjacent cells) and in dynamic patterns of control sequences (what were the sequences of reads and writes) combined with patterns of data bits. PABIST allowed more complex testing but a simple input/output compare with a pass/fail was no longer always possible. What was written to an address may not be what was read at the next cycle, a different address may be read, or a read complement of the data may be executed in an attempt to exercise all of the potential failure modes of the array.
To deal with these complexities, designers implemented xe2x80x9csignaturexe2x80x9d testing. In signature testing, test patterns and sequences of reads and writes would be simulated and, since the correct output at each read was known, a signature of the expected outputs could be generated. When the same test patterns and sequences were applied to an array, the read outputs were outputted and compared to the known xe2x80x9csignaturexe2x80x9d to determine if the array was functioning correctly. A pass/fail on each array was not possible because the expected result on the array out was not generated in the ABIST engine.
While programmable PABIST has brought improvements, the ability to generate very complex data patterns and sequences of operations on an array has outstripped the ability of the test method and hardware to simply analyze the results because of the complexity required to determine expected outputs for compare; the potential of PABIST has been limited.
Clearly there is a need to improve the programmable ABIST system to deal with increased array complexity and the complexity of test patterns and sequences needed to test the failure modes of the arrays.
The present invention adds a programmable expect generator to a programmable Array Built-In Test (PABIST) system to generate data patterns to compare to the outputs of an array that is under test. Prior art PABIST systems sometimes do a simple write of data to an array address followed by a read of the data written. In this simple case the input data written at an address is the data xe2x80x9cexpectedxe2x80x9d when data is read from the corresponding same address. In dense VLSI arrays, failure modes depend not only on the bits adjacent to a given bit in all spacial directions but also on what operation sequences preceded or came after writing or reading a given bit. In these complex tests it is not possible to test an array with a simple write then read and compare at a given address. PABIST systems have employed a form of signature testing to handle these test cases. The present invention discloses the use of a programmable expect generator (PEG), which is, in one embodiment, a duplicate of the data control register used to generate input data patterns for a PABIST system. The PEG has separate control lines and while the PEG receives the same type of programming commands synchronous with the data control register, in general it receives a different control sequence than the data control register in the same PABIST system. In many cases the PEG can be programmed to generate the sequence of data outputs expected from an array undergoing a complex input address, data and read/write control sequence. This program for the PEG for a given test is determined beforehand along with the program for the PABIST controller generating the test sequence. The PEG also has a corresponding mask bit with each program step that controls whether a compare is enabled on each array data output sequence step. If a test sequence does not allow all of the sequential states of array outputs to be compared within a single corresponding sequence of PEG program steps, those sequences not testable are masked and a separate pass of the test sequence can be run with a different PEG program which will generate expected outputs for missed sequences. The PEG allows pass/fail testing of complex input data patterns and corresponding read/write sequences not previously possible with PABIST.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.